Design and analysis of High-Speed Low-Power Vedic Multiplier with 3-1-1-2 compressor Using Reversible Logic gates
نویسندگان
چکیده
منابع مشابه
Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics
High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...
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ژورنال
عنوان ژورنال: IOP Conference Series: Materials Science and Engineering
سال: 2021
ISSN: 1757-8981,1757-899X
DOI: 10.1088/1757-899x/1059/1/012024